The present invention relates to a method for fabricating an MIS semiconductor device that has a superfine structure contributing to ultralarge-scale integration of a semiconductor integrated circuit and that can operate at a high speed with its power dissipation reduced.
As ultralarge-scale integration of semiconductor integrated circuits advances, miniaturization of MIS transistors is demanded more and more strongly. For that purpose, an MIS transistor with a shallow junction is now in high demand.
FIG. 10 illustrates a cross-sectional structure for a known MIS transistor with a shallow junction. A gate electrode 3 has been formed over a p-type semiconductor substrate 1 with a gate insulating film 2 interposed therebetween. In respective surface regions of the semiconductor substrate 1 that are located on both sides of the gate electrode 3 (i.e., regions to be source/drain regions), high-concentration dopant diffused layer 5, extended high-concentration dopant diffused layer 6 and pocket dopant diffused layer 7 have been formed. The high-concentration dopant diffused layer 5 is formed to have a deep junction by diffusing an n-type dopant (e.g., arsenic) thereto. The extended high-concentration dopant diffused layer 6 is formed inside the high-concentration dopant diffused layer 5 by diffusing an n-type dopant (e.g., arsenic) thereto and has a junction shallower than that of the high-concentration dopant diffused layer 5. And the pocket dopant diffused layer 7 is located under the extended high-concentration dopant diffused layer 6 and has been formed by diffusing a p-type dopant (e.g., boron) thereto. Also, a sidewall 8 has been formed out of an insulating film on the side faces of the gate electrode 3.
Hereinafter, a method for fabricating the known MIS transistor will be described with reference to FIGS. 11(a) through 11(e).
First, as shown in FIG. 11(a), a gate electrode 3 of polysilicon is formed over a p-type semiconductor substrate 1 with a gate insulating film 2 interposed therebetween.
Next, ions of arsenic and boron, which are n- and p-type dopants, respectively, are implanted in this order using the gate electrode 3 as a mask, thereby forming an n-type high-concentration dopant layer 6A and a p-type-ion implanted layer 7A, respectively, as shown in FIG. 11(b).
Then, a silicon nitride film is deposited over the entire surface of the semiconductor substrate 1 at a temperature of about 700xc2x0 C., and then etched anisotropically, thereby forming a sidewall 8 on the side faces of the gate electrode 3 as shown in FIG. 11(c).
Subsequently, ions of arsenic as an n-type dopant are implanted using the gate electrode 2 and sidewall 8 as a mask. Then, annealing is conducted at a temperature between about 900xc2x0 C. and about 1000xc2x0 C. for about 10 seconds. In this manner, n-type high-concentration dopant diffused layer 5 with a deep junction, n-type extended high-concentration dopant diffused layer 6 located inside the high-concentration dopant diffused layer 5 and having a junction shallower than that of the high-concentration dopant diffused layer 5 and p-type pocket dopant diffused layer 7 located under the extended high-concentration dopant diffused layer 6 are formed as shown in FIG. 11(d).
Thereafter, a cobalt film and a titanium nitride film are deposited in this order to thicknesses of about 10 nm and about 20 nm, respectively, over the semiconductor substrate 1 by a sputtering process. Next, annealing is conducted at a temperature of about 550xc2x0 C. for about 10 seconds. Then, the titanium nitride film and unreacted parts of the cobalt film are selectively etched away using a mixture of sulfuric acid, hydrogen peroxide and water. And then annealing is conducted at a temperature of about 800xc2x0 C. for about 10 seconds. In this manner, a cobalt silicide layer 9 is formed to a thickness of about 30 nm on respective surfaces of the gate electrode 3 and high-concentration dopant diffused layer 5 in a self-aligned manner as shown in FIG. 11(e).
In the known MIS transistor fabrication process, the implant energy of arsenic ions for the n-type-ion implanted layer 6A to be the extended high-concentration dopant diffused layer 6 is lowered to make the junction of the extended high-concentration dopant diffused layer 6 shallower and thereby increase the driving power of the MIS transistor. Also, to reduce the parasitic resistance of the source/drain regions, the implant dose of the arsenic ions is normally increased in this case.
However, if the n-type-ion implanted layer 6A is formed by implanting the arsenic ions at a high implant dose and with a low implant energy, then transient enhanced diffusion (TED) of arsenic (i.e., dopant for the n-type-ion implanted layer 6A) occurs as a result of the low-temperature (e.g., about 700xc2x0 C.) annealing process to be carried out to form the sidewall 8. In that case, the extended high-concentration dopant diffused layer 6 cannot be formed to have a shallow junction as designed. As used herein, the transient enhanced diffusion is a phenomenon in which an introduced dopant unintentionally diffuses at such a rate as exceeding its diffusion coefficient in thermal equilibrium state. This is because point defects, existing in excessive numbers between lattice sites, and the dopant interact with each other to mutually enhance their diffusion.
FIG. 12 illustrates profiles of the dopants, which have been introduced to form the extended high-concentration dopant diffused layer 6 and pocket dopant diffused layer 7, in the depth direction (i.e., the direction indicated by the line A-Axe2x80x2 in FIG. 10). As can be seen from FIG. 12, the profile of arsenic for the extended high-concentration dopant diffused layer 6 as plotted in the depth direction shows that its diffusion is rather deep due to the transient enhanced diffusion effects during the anneal. Boron for the pocket dopant diffused layer 7 has also been much affected by the transient enhanced diffusion so that its profile has lost steepness. As also can be seen from FIG. 12, according to the known method, it is difficult to form the extended high-concentration dopant diffused layer 6 and pocket dopant diffused layer 7 just as intended, i.e., so that these layers are shallow and steep enough and exhibit excellent short channel effects.
In view of the foregoing, an object of the present invention is providing a method for fabricating a semiconductor device that can shallow the junction depth of the extended high-concentration dopant diffused layer and can minimize increase in leakage current.
To achieve this object, a first inventive method for fabricating a semiconductor device includes the steps of: forming a gate electrode over a semiconductor region with a gate insulating film interposed therebetween; forming an amorphous layer in the semiconductor region by implanting heavy ions with a large mass into the semiconductor region using the gate electrode as a mask; implanting ions of a first dopant into the semiconductor region using the gate electrode as a mask; conducting a first annealing process on the semiconductor region at a temperature between 400xc2x0 C. and 550xc2x0 C., thereby making the amorphous layer recover into a crystalline layer; and conducting a second annealing process on the semiconductor region, thereby forming an extended high-concentration dopant diffused layer of a first conductivity type and a pocket dopant diffused layer of a second conductivity type. The extended high-concentration dopant diffused layer is formed to have a shallow junction by diffusing the first dopant, while the pocket dopant diffused layer is formed under the extended high-concentration dopant diffused layer by diffusing the heavy ions.
In the first method for fabricating a semiconductor device, after an amorphous layer has been formed in a semiconductor region by implanting heavy ions with a large mass that will make a pocket dopant diffused layer, ions of a first dopant are implanted. Accordingly, channeling of the first dopant is avoidable and therefore the extended high-concentration dopant diffused layer can have a shallower junction. As a result, a transistor can be downsized without decreasing the driving power thereof.
Also, after the heavy ions and ions of a first dopant, which will make the pocket dopant diffused layer and extended high-concentration dopant diffused layer, respectively, have been implanted, an annealing process is conducted at a temperature between 400xc2x0 C. and 550xc2x0 C., thereby recovering the crystallinity of the semiconductor region. And then the extended high-concentration dopant diffused layer and pocket dopant diffused layer are formed by activating the first dopant and heavy ions. Accordingly, no amorphous/crystalline interface or no dislocation loop layer is formed in the extended high-concentration dopant diffused layer and pocket dopant diffused fused layer. Thus, it is possible to avoid a situation where dopant atoms are trapped and segregate in the dislocation loop layer. As a result, leakage current, caused by the dislocation loop layer, can be reduced.
A second inventive method for fabricating a semiconductor device includes the steps of: forming a gate electrode over a semiconductor region with a gate insulating film interposed therebetween; repeatedly performing, a number of times, the steps of implanting, using the gate electrode as a mask, heavy ions with a large mass into the semiconductor region at such an implant dose as forming no amorphous layers and conducting a first annealing process on the semiconductor region at an elevated temperature for a short period of time; implanting ions of a first dopant into the semiconductor region using the gate electrode as a mask; and conducting a second annealing process on the semiconductor region, thereby forming an extended high-concentration dopant diffused layer of a first conductivity type and a pocket dopant diffused layer of a second conductivity type. The extended high-concentration dopant diffused layer is formed to have a shallow junction by diffusing the first dopant, while the pocket dopant diffused layer is formed under the extended high-concentration dopant diffused layer by diffusing the heavy ions.
In the second method for fabricating a semiconductor device, heavy ions with a large mass, which will make a pocket dopant diffused layer, are repeatedly implanted a number of times at such an implant dose as forming no amorphous layers each time. Thus, no amorphous layers are formed in the semiconductor region and therefore no amorphous/crystalline interface or no dislocation loop layer will be formed, either. Thus, it is possible to avoid a situation where dopant atoms are trapped and segregate in the dislocation loop layer. As a result, leakage current, caused by the dislocation loop layer, can be reduced. Since no dislocation loop layer is formed, leakage current decreases. Consequently, a semiconductor device can be fabricated using the heavy ions so as to have a shallower junction depth and a reduced junction leakage current.
Although the implant dose is set relatively low for each implantation process of the heavy ions, the heavy ions are implanted several times. Thus, the dopant concentration of the pocket dopant diffused layer will not be lower than expected.
Furthermore, every time the heavy ions are implanted, a rapid thermal annealing process is conducted at an elevated temperature for just a short period of time. Thus, the damage done on the crystals in the semiconductor region due to the heavy ion implantation does not accumulate but can be repaired each time. Accordingly, the leakage current can be further reduced.
A third inventive method for fabricating a semiconductor device includes the steps of: forming a gate electrode over a semiconductor region with a gate insulating film interposed therebetween; forming an amorphous layer in the semiconductor region by implanting heavy ions with a large mass into the semiconductor region using the gate electrode as a mask; implanting ions of a first dopant into the semiconductor region using the gate electrode as a mask; implanting ions of a Group IV element into the semiconductor region using the gate electrode as a mask, thereby lowering the amorphous layer to a deeper level in a substrate; and conducting a second annealing process on the semiconductor region, thereby forming an extended high-concentration dopant diffused layer of a first conductivity type and a pocket dopant diffused layer of a second conductivity type. The extended high-concentration dopant diffused layer is formed to have a shallow junction by diffusing the first dopant, while the pocket dopant diffused layer is formed under the extended high-concentration dopant diffused layer by diffusing the heavy ions.
In the third method for fabricating a semiconductor device, after an amorphous layer has been formed in a semiconductor region by implanting heavy ions with a large mass that will make a pocket dopant diffused layer, ions of a first dopant are implanted. Accordingly, channeling of the first dopant is avoidable and therefore the extended high-concentration dopant diffused layer can have a shallower junction. As a result, a transistor can be downsized without decreasing the driving power thereof.
Also, after the heavy ions and ions of the first dopant, which will make the pocket dopant diffused layer and extended high-concentration dopant diffused layer, respectively, have been implanted, ions of a Group IV element are implanted to lower the level of the amorphous layer deeper into the substrate. And then the extended high-concentration dopant diffused layer and pocket dopant diffused layer are formed by activating the first dopant and heavy ions. Accordingly, no amorphous/crystalline interface or no dislocation loop layer is formed in the extended high-concentration dopant diffused layer and pocket dopant diffused layer. Thus, it is possible to avoid a situation where dopant ions segregate in the dislocation loop layer. As a result, leakage current can be reduced.
Furthermore, after the amorphous layer has been lowered to a deeper level in the substrate, the extended high-concentration dopant diffused layer and pocket dopant diffused layer are formed. Thus, annealing can be performed with the amorphous/crystalline interface moved to a level far away from a region that will affect the transistor electrically. For that reason, even if the rapid thermal annealing is carried out while the amorphous/crystalline interface exists, the dislocation loop layer will be formed at a level much distant from the vicinity of the junction. Accordingly, the leakage current is suppressible.
Moreover, since the dislocation loop layer is also located at a level far away from the high-concentration region of the heavy ions, it is possible to suppress the heavy ions from being deposited in the dislocation loop layer.
A fourth inventive method for fabricating a semiconductor device includes the steps of: forming a gate electrode over a semiconductor region with a gate insulating film interposed therebetween; forming an extended high-concentration dopant diffused layer of a first conductivity type through diffusion of heavy ions with a large mass by repeatedly performing, a number of times, the steps of implanting, using the gate electrode as a mask, the heavy ions into the semiconductor region at such an implant dose as forming no amorphous layers and conducting an annealing process on the semiconductor region at an elevated temperature for a short period of time; forming a sidewall on side faces of the gate electrode and then implanting ions of a dopant into the semiconductor region using the gate electrode and the sidewall as a mask; and activating and diffusing the dopant, thereby forming a high-concentration dopant diffused layer of the first conductivity type, which is located outside of the extended high-concentration dopant diffused layer and has a deep junction.
In the fourth method for fabricating a semiconductor device, heavy ions with a large mass, which will make an extended high-concentration dopant diffused layer, are implanted at such an implant dose as forming no amorphous layers. Accordingly, no amorphous layers will be formed in the semiconductor region, and no amorphous/crystalline interface or no dislocation loop layer will be formed, either. Thus, it is possible to avoid a situation where heavy ions segregate in the dislocation loop layer. As a result, leakage current can be reduced. Since no dislocation loop layer is formed, leakage current decreases. Consequently, a semiconductor device can be fabricated using the heavy ions so as to have a shallower junction depth and a reduced junction leakage current.
Although the implant dose is set relatively low for each heavy ion implantation process, the heavy ions are implanted several times. Thus, the dopant concentration of the pocket dopant diffused layer will not be lower than expected.
Furthermore, every time the heavy ions are implanted, a rapid thermal annealing process is conducted at an elevated temperature for just a short period of time. Thus, the damage done on the crystals in the semiconductor region due to the heavy ion implantation does not accumulate but can be repaired each time. Accordingly, the leakage current can be further reduced.